Z51F0410 Datasheet, PDF (102/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
4.6.4 External Clock (XCK)
External clocking is used by the synchronous or spi slave modes of operation.
External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability.
The output from the synchronization logic must then pass through an edge detector before it can be
used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and
therefore the maximum frequency of the external XCK pin is limited by the following equation.
fXCK
fSCLK
4
where fXCK is the frequency of XCK and fSCLK is the frequency of main system clock (SCLK).
4.6.5 Synchronous mode operation
When synchronous or spi mode is used, the XCK pin will be used as either clock input (slave) or
clock output (master). The dependency between the clock edges and data sampling or data change is
the same. The basic principle is that data input on RXD (MISO in spi mode) pin is sampled at the
opposite XCK clock edge of the edge in the data output on TXD (MOSI in spi mode) pin is changed.
The UCPOL bit in UCTRL1 register selects which XCK clock edge is used for data sampling and
which is used for data change. As shown in the figure below, when UCPOL is zero the data will be
changed at rising XCK edge and sampled at falling XCK edge.
UCPOL = 1
XCK
TXD/RXD
UCPOL = 0
XCK
Sample
TXD/RXD
Sample
4.6.6 Data format
Figure 4.20 Synchronous Mode XCKn Timing.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking.
The USART supports all 30 combinations of the following as valid frame formats.
- 1 start bit
- 5, 6, 7, 8 or 9 data bits
- no, even or odd parity bit
- 1 or 2 stop bits
PS029502-0212
PRELIMINARY
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