Z51F0410 Datasheet, PDF (11/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Figure 6.10 Internal Reset at the power fail situation........................................................................ 148
Figure 6.11 Configuration timing when BOD RESET........................................................................ 148
Figure 7.1 Block Diagram of On-chip Debug System ....................................................................... 150
Figure 7.2 10-bit transmission packet ............................................................................................... 151
Figure 7.3 Data transfer on the twin bus........................................................................................... 152
Figure 7.4 Bit transfer on the serial bus ............................................................................................ 152
Figure 7.5 Start and stop condition................................................................................................... 152
Figure 7.6 Acknowledge on the serial bus ........................................................................................ 153
Figure 7.7 Clock synchronization during wait procedure .................................................................. 153
Figure 7.8 Connection of transmission ............................................................................................. 154
Figure 8.1 Flash Memory Map.......................................................................................................... 160
Figure 8.2 Address configuration of Flash memory .......................................................................... 160
Figure 8.3 Data EEPROM memory map........................................................................................... 161
Figure 8.4 Address configuration of data EEPROM.......................................................................... 161
Figure 8.5 The sequence of page program and erase of Flash memory .......................................... 162
Figure 8.6 The sequence of bulk erase of Flash memory ................................................................. 163
Figure 8.7 Pin diagram for parallel programming.............................................................................. 169
Figure 8.8 Parallel Byte Read Timing of Program Memory............................................................... 171
Figure 8.9 Parallel Byte Write Timing of Program Memory ............................................................... 171
Figure 8.10 ISP mode ..................................................................................................................... 172
Figure 8.11 Byte-parallel mode (10pin package only)....................................................................... 172
PS029502-0212
PRELIMINARY
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