Z51F0410 Datasheet, PDF (123/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00
into I2CSDAHR to make SDA change within one system clock period from the falling edge of
SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is
multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer
than the period of SCLK, I2C (slave) cannot transmit serial data properly.
2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the
peripheral.
3. When a START condition is detected, I2C receives one byte of data and compares it with
SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received
data with value 0x00, the general call address.
Note: General call interrupt can occur as though the received data does not match the
general call address. When general call interrupt happens, I2CDR must be checked to match
0x00.
4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits
for another START condition. Else if the address equals to SLA bits and the ACKEN bit is
enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the
address equals to SLA bits, when the ACKEN bit is disabled, I2C enters idle state. When
SSEL interrupt occurs, load transmit data to I2CDR and write arbitrary value to I2CSR to
release SCL line.
5. 1-Byte of data is being transmitted.
6. In this step, I2C generates TEND interrupt and holds the SCL line LOW regardless of the
reception of ACK signal from master. Slave can select one of the following cases.
1) No ACK signal is detected and I2C waits STOP or repeated START condition.
2) ACK signal from master is detected. Load data to transmit into I2CDR.
After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either
case, a repeated START condition can be detected. For that case, move step 4.
7. This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOP
bit indicates that data transfer between master and slave is over. To clear I2CSR, write
arbitrary value to I2CSR. After this, I2C enters idle state.
The next figure shows flow chart for handling slave transmitter function of I2C.
PS029502-0212
PRELIMINARY
120