Z51F0410 Datasheet, PDF (111/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
UCPOL
0
0
1
1
UCPHA
0
1
0
1
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
UCTRL2 (USART Control 2 Register) : E3H
7
6
5
4
3
UDRIE
TXCIE
RXCIE
WAKEIE
TXE
R/W
R/W
R/W
R/W
R/W
2
1
0
RXE
USARTEN
U2X
R/W
R/W
R/W
Initial value : 00H
UDRIE
TXCIE
RXCIE
WAKEIE
TXE
RXE
USARTEN
U2X
Interrupt enable bit for USART Data Register Empty.
0
Interrupt from UDRE is inhibited (use polling)
1
When UDRE is set, request an interrupt
Interrupt enable bit for Transmit Complete.
0
Interrupt from TXC is inhibited (use polling)
1
When TXC is set, request an interrupt
Interrupt enable bit for Receive Complete
0
Interrupt from RXC is inhibited (use polling)
1
When RXC is set, request an interrupt
Interrupt enable bit for Asynchronous Wake in STOP mode. When device
is in stop mode, if RXD goes to LOW level an interrupt can be requested
to wake-up system.
0
Interrupt from Wake is inhibited
1
When WAKE is set, request an interrupt
Enables the transmitter unit.
0
Transmitter is disabled
1
Transmitter is enabled
Enables the receiver unit.
0
Receiver is disabled
1
Receiver is enabled
Activate USART module by supplying clock.
0
USART is disabled (clock is halted)
1
USART is enabled
This bit only has effect for the asynchronous operation and selects
receiver sampling rate.
0
Normal asynchronous operation
1
Double Speed asynchronous operation
UCTRL3 (USART Control 3 Register) : E4H
7
6
5
4
3
2
1
0
MASTER
LOOPS
DISXCK
SPISS
-
USBS
TX8
RX8
R/W
R/W
R/W
R/W
-
R/W
R/W
R/W
Initial value : 00H
MASTER
Selects master or slave in SPI or Synchronous mode operation and
controls the direction of XCK pin.
0
Slave mode operation and XCK is input pin.
1
Master mode operation and XCK is output pin
PS029502-0212
PRELIMINARY
108