Z51F0410 Datasheet, PDF (124/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
LOST&
IDLE
S or Sr
SLA+R
0x97
0x1F
ACK
Y
0x17
GCALL
DATA
Y
0x47
ACK
Y
N
0x46
0x22
STOP
P
IDLE
From master to slave /
Master command or Data Write
From slave to master
0xxx _{Value of Status Register}
ACK ^{Interrupt, SCL line is held low}
P Interrupt after stop command
LOST&
Arbitration lost as master and
addressed as slave
GCALL General Call Address
Figure 4.36 Formats and States in the Slave Transmitter Mode
4.7.8.4 Slave Receiver
To operate I2C in slave receiver, follow the recommended steps below.
1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00
into I2CSDAHR to make SDA change within one system clock period from the falling edge of
SCL. Note that the hold time of SDA is calculated by SDAH x period of SCLK where SDAH is
multiple of number of SCLK coming from I2CSDAHR. When the hold time of SDA is longer
than the period of SCLK, I2C (slave) cannot transmit serial data properly.
2. Enable I2C by setting IICEN bit and INTEN bit in I2CMR. This provides main clock to the
peripheral.
3. When a START condition is detected, I2C receives one byte of data and compares it with
SLA bits in I2CSAR. If the GCALLEN bit in I2CSAR is enabled, I2C compares the received
data with value 0x00, the general call address.
4. If the received address does not equal to SLA bits in I2CSAR, I2C enters idle state ie, waits
for another START condition. Else if the address equals to SLA bits and the ACKEN bit is
enabled, I2C generates SSEL interrupt and the SCL line is held LOW. Note that even if the
PS029502-0212
PRELIMINARY
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