Z51F0410 Datasheet, PDF (38/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11.7 P0[6]/P0[7] Port Structure
Output
Input
Secondary
Analog
Input
FUSE_PKG8
(from Config)
Pull-up Enable
Open-Drain
Output Data
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
PCI_EN[6]/PCI_EN[7]
PCI_IN[6]/PCI_IN[7]
AN6/AN7
AN6_EN/AN7_EN
Z51F0410
Product Specification
VDD
VDD
1
0
LPF
R0[6]/AN6
P0[7]/AN7
Figure 1.24 P0[6] / AN6, P0[7] / AN7 Port Structure
The analog channel selection bit enables the path of the AN6/AN7 and disable normal logic data path
to prevent the input gate leakage current. When the direction register value is 0, the input data is
always external PAD voltage.
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. When the direction is output (value 1), the output PAD voltage is controlled by push-pull
driver for the current output data. The secondary input PCI_EN[6]/PCI_EN[7] enable the input data
path continuously. On normal read mode (non secondary mode), the input data path is only enabled
during the CPU OEB (active low). When the analog channel (AN6/AN7) is enabled, the first input gate
from the PAD is disabled (highest priority) to prevent the input leakage current for the floating voltage
status. At read operation, the input data is selected by PAD direction register. If its value is ‘1’, it reads
the current output register value. Otherwise, it reads the current PAD voltage directly (just during OEB
active). In addition, always the current PAD voltage is read by PAD DATA register.
PS029502-0212
PRELIMINARY
35