Z51F0410 Datasheet, PDF (112/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
LOOPS
DISXCK
SPISS
USBS
TX8
RX8
Controls the Loop Back mode of USART, for test mode
0
Normal operation
1
Loop Back mode
In Synchronous mode of operation, selects the waveform of XCK output.
0
XCK is free-running while USART is enabled in synchronous
master mode.
1
XCK is active while any frame is on transferring.
Controls the functionality of SS pin in master SPI mode.
0
SS pin is normal GPIO or other primary function
1
SS output to other slave device
Selects the length of stop bit in Asynchronous or Synchronous mode of
operation.
0
1 Stop Bit
1
2 Stop Bit
The ninth bit of data frame in Asynchronous or Synchronous mode of
operation. Write this bit first before loading the UDATA register.
0
MSB (9^th bit) to be transmitted is ‘0’
1
MSB (9^th bit) to be transmitted is ‘1’
The ninth bit of data frame in Asynchronous or Synchronous mode of
operation. Read this bit first before reading the receive buffer.
0
MSB (9^th bit) received is ‘0’
1
MSB (9^th bit) received is ‘1’
USTAT (USART Status Register) : E5H
7
UDRE
R/W
6
5
4
3
2
TXC
RXC
WAKE
SOFTRST
DOR
R/W
R/W
R/W
R/W
R
1
0
FE
PE
R
R
Initial value : 80H
UDRE
TXC
RXC
WAKE
SOFTRST
The UDRE flag indicates if the transmit buffer (UDATA) is ready to
receive new data. If UDRE is ‘1’, the buffer is empty and ready to be
written. This flag can generate a UDRE interrupt.
0
Transmit buffer is not empty.
1
Transmit buffer is empty.
This flag is set when the entire frame in the transmit shift register has
been shifted out and there is no new data currently present in the
transmit buffer. This flag is automatically cleared when the interrupt
service routine of a TXC interrupt is executed. This flag can generate a
TXC interrupt.
0
Transmission is ongoing.
1
Transmit buffer is empty and the data in transmit shift register
are shifted out completely.
This flag is set when there are unread data in the receive buffer and
cleared when all the data in the receive buffer are read. The RXC flag
can be used to generate a RXC interrupt.
0
There is no data unread in the receive buffer
1
There are more than 1 data in the receive buffer
This flag is set when the RX pin is detected low while the CPU is in stop
mode. This flag can be used to generate a WAKE interrupt. This bit is set
only when in asynchronous mode of operation.
0
No WAKE interrupt is generated.
1
WAKE interrupt is generated
This is an internal reset and only has effect on USART. Writing ‘1’ to this
PS029502-0212
PRELIMINARY
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