Z51F0410 Datasheet, PDF (34/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
1.11.5 P0[4] Port Structure
Output
Input
Secondary
Input
Pull-up Enable
I2C_EN
PIN_MODE0
Open-Drain
Output Data
0
0
SCL_OUT ¹
T0O
1
I2C_EN
T0O_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
I2C_EN
SCL_IN
PCI_EN[4]
PCI_IN[4]
Analog
Input
AN4
AN4_EN
AC-
AC- EN
AVREF
AVREF_EN
VDD
VDD
P04 / SCL / T0O /
AN4 / AC- / AVref
1
0
LPF
Figure 1.22 P0[4]/SCL/T0O/AN4/AC-/Avref Port Diagram
The pull-up resister is directly controlled by the pull-up register bit regardless of current port direction.
The open-drain control is also by open-drain register. On open-drain mode, the push-pull drives just
N-MOS. The I2C Mode enable the Open-drain Output regardless of the Open-Drain Register value.
When the direction is output (value 1), the output PAD voltage is controlled by push-pull driver for the
current output data. The secondary input or analog channel selection bit disable the output direction
regardless of the current direction register. The secondary input SCL_IN_EN, PCI_EN[4] enables the
input data path continuously. On normal read mode (non secondary mode), the input data path is only
enabled during the CPU OEB (active low). When the analog channel (AN4,AC-) is enabled, the first
input gate from the PAD is disabled (highest priority) to prevent the input leakage current for the
floating voltage status. The AVREF function disables all analog channels and secondary
PS029502-0212
PRELIMINARY
31