Z51F0410 Datasheet, PDF (118/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
will switch off its DATA output state because the level on the bus doesn’t correspond to its own level.
Arbitration continues for many bits until a winning master gets the ownership of I2C bus. Its first stage
is comparison of the address bits.
Fast Device
SCLOUT
Low Device
SCLOUT
SCL
Wait High
Counting
Start High
Counting
High Counter
Reset
Figure 4.32 Clock Synchronization during Arbitration Procedure
Device1
DataOut
Arbitration Process
not adaped
Device2
DataOut
SDA on BUS
Device 1 loses
Arbitration
Device1 outputs
High
SCL on BUS
S
Figure 4.33 Arbitration Procedure of Two Masters
4.7.8 OPERATION
The I2C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a
transmission of a START condition. Because the I2C is interrupt based, the application software is
free to carry on other operations during a I2C byte transfer.
Note that when a I2C interrupt is generated, IIF flag in I2CMR register is set, it is cleared by writing
an arbitrary value to I2CSR. When I2C interrupt occurs, the SCL line is hold LOW until writing any
value to I2CSR. When the IIF flag is set, the I2CSR contains a value indicating the current state of the
I2C bus. According to the value in I2CSR, software can decide what to do next.
I2C can operate in 4 modes by configuring master/slave, transmitter/receiver. The operating mode
is configured by a winning master. A more detailed explanation follows below.
PS029502-0212
PRELIMINARY
115