Z51F0410 Datasheet, PDF (59/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
3. Interrupt Controller
3.1 Overview
The Z51F0410 MCU supports up to 15 interrupt sources. The interrupts have separate enable
register bits associated with them, allowing software control. They can also have four levels of priority
assigned to them. The nonmaskable interrupt source is always enabled with a higher priority than any
other interrupt source, and is not controllable by software. The interrupt controller has following
features:
- receive the request from 24 interrupt source
- 6 group priority
- 4 priority levels
- Multi Interrupt possibility
- If the requests of different priority levels are received simultaneously, the request of higher
priority level is serviced
- Each interrupt source can control by EA bit and each IEx bit
- Interrupt latency: 5–8 machine cycles in single interrupt system
The nonmaskable interrupt is always enabled. The maskable interrupts are enabled through four pair
of interrupt enable registers (IE, IE1, IE2, IE3). Bits of IE, IE1, IE2, IE3 register each individually
enable/disable a particular interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is
set to ‘0’, all interrupts are disabled: when EA is set to ‘1’, interrupts are individually enabled or
disabled through the other bits of the interrupt enable registers. The Z51F0410 MCU supports a four-
level priority scheme. Each maskable interrupt is individually assigned to one of four priority levels by
writing to IP or IP1.
External interrupt default mode is level-trigger basically but if needed, it is able to change edge-
trigger mode. Table 3.1 shows the Interrupt Group Priority Level that is available for sharing interrupt
priority. Priority sets two bit which is to IP and IP1 register about group. Interrupt service routine
services higher priority. If two requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If the request of same or lower priority level is received, that
request is not serviced.
Table 3.1 Interrupt Group Priority Level
Interrupt Highest
Group
Lowest
0 (Bit0) Interrupt0 Interrupt6 Interrupt12 Interrupt18
1 (Bit0) Interrupt1 Interrupt7 Interrupt13 Interrupt19
2 (Bit0) Interrupt2 Interrupt8 Interrupt14 Interrupt20
3 (Bit0) Interrupt3 Interrupt9 Interrupt15 Interrupt21
4 (Bit0) Interrupt4 Interrupt10 Interrupt16 Interrupt22
5 (Bit0) Interrupt5 Interrupt11 Interrupt17 Interrupt23
Highest
Lowest
3.2 External Interrupt
The external interrupt on INT0, INT1 pins receive various interrupt request depending on the edge
selection register EIEDGE (External Interrupt Edge register) and EIPOLA (External Interrupt Polarity
register) as shown in Figure 3.1. Also each external interrupt source has control setting bits. The
PS029502-0212
PRELIMINARY
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