Z51F0410 Datasheet, PDF (104/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Note: In Tx mode, the length of start bit can be shorter than one or two clock of the lengh of the other
data bits.
4.6.8.1 Sending Tx data
A data transmission is initiated by loading the transmit buffer (UDATA register I/O location) with the
data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift
register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state
or immediately after the last stop bit of the previous frame is transmitted. When the shift register is
loaded with new data, it will transfer one complete frame at the settings of control registers. If the 9-bit
characters are used in asynchronous or synchronous operation mode (USIZE[2:0]=7), the ninth bit
must be written to the TX8 bit in UCTRL3 register before loading transmit buffer (UDATA register).
4.6.8.2 Transmitter flag and interrupt
The USART Transmitter has 2 flags which indicate its state. One is USART Data Register Empty
(UDRE) and the other is Transmit Complete (TXC). Both flags can be interrupt sources.
UDRE flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the
transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has
not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit
position. Writing ‘1’ to this bit position is prevented.
When the Data Register Empty Interrupt Enable (UDRIE) bit in UCTRL2 register is set and the
Global Interrupt is enabled, USART Data Register Empty Interrupt is generated while UDRE flag is
set.
The Transmit Complete (TXC) flag bit is set when the entire frame in the transmit shift register has
been shifted out and there are no more data in the transmit buffer. The TXC flag is automatically
cleared when the Transmit Complete Interrupt service routine is executed, or it can be cleared by
writing ‘0’ to TXC bit in UCTRL2 register.
When the Transmit Complete Interrupt Enable (TXCIE) bit in UCTRL2 register is set and the Global
Interrupt is enabled, USART Transmit Complete Interrupt is generated while TXC flag is set.
4.6.8.3 Parity Generator
The Parity Generator calculates the parity bit for the sending serial frame data. When parity bit is
enabled (UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first
stop bit of the sending frame.
4.6.8.4 Disabling Transmitter
Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission
is completed. When the Transmitter is disabled, the TXD pin is used as normal General Purpose I/O
(GPIO) or primary function pin.
4.6.9 USART Receiver
The USART Receiver is enabled by setting the RXE bit in the UCTRL1 register. When the Receiver
is enabled, the normal pin operation of the RXD pin is overridden by the USART as the serial input pin
of the Receiver. The baud-rate, mode of operation and frame format must be set before serial
reception. If synchronous or spi operation is used, the clock on the XCK pin will be used as transfer
clock. If USART operates in spi mode, SS pin is used as SS input pin in slave mode or can be
PS029502-0212
PRELIMINARY
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