Z51F0410 Datasheet, PDF (109/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
XCK
(UCPOL=0)
XCK
(UCPOL=1)
SAMPLE
MOSI
MSB First
LSB First
MISO
/SS OUT
(MASTER)
/SS IN
(SLAVE)
BIT7
BIT0
BIT6
BIT1
…
BIT2
BIT1
BIT0
…
BIT5
BIT6
BIT7
Figure 4.26 SPI Clock Formats when UCPHA=1
When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data
is not defined until the first XCK edge. The first XCK edge shifts the first bit of data from the shifter
onto the MOSI output of the master and the MISO output of the slave. The next XCK edge causes
both the master and slave to sample the data bit value on their MISO and MOSI inputs, respectively.
At the third XCK edge, the USART shifts the second data bit value out to the MOSI and MISO output
of the master and slave respectively. When UCPHA=1, the slave’s SS input is not required to go to its
inactive high level between transfers.
Because the SPI logic reuses the USART resources, SPI mode of operation is similar to that of
synchronous or asynchronous operation. An SPI transfer is initiated by checking for the USART Data
Register Empty flag (UDRE=1) and then writing a byte of data to the UDATA Register. In master
mode of operation, even if transmission is not enabled (TXE=0), writing data to the UDATA register is
necessary because the clock XCK is generated from transmitter block.
4.6.11 Register Map
Name
UCTRL1
UCTRL2
UCTRL3
USTAT
UBAUD
UDATA
Address
E2H
E3H
E4H
E5H
E6H
E7H
Table 4.11 USART Register Map
Dir
R/W
R/W
R/W
R
R/W
R/W
Default
00H
00H
00H
80H
FFH
FFH
Description
USART Control 1 Register
USART Control 2 Register
USART Control 3 Register
USART Status Register
USART Baud Rate Generation Register
USART Data Register
PS029502-0212
PRELIMINARY
106