Z51F0410 Datasheet, PDF (105/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
configured as SS output pin in master mode. This can be done by setting SPISS bit in UCTRL3
register.
4.6.9.1 Receiving Rx data
When USART is in synchronous or asynchronous operation mode, the Receiver starts data
reception when it detects a valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at pre-
defined baud-rate (asynchronous) or sampling edge of XCK (synchronous), and shifted into the
receive shift register until the first stop bit of a frame is received. Even if there’s 2^nd stop bit in the
frame, the 2^nd stop bit is ignored by the Receiver. That is, receiving the first stop bit means that a
complete serial frame is present in the receiver shift register and contents of the shift register are to
be moved into the receive buffer. The receive buffer is read by reading the UDATA register.
If 9-bit characters are used (USIZE[2:0] = 7) the ninth bit is stored in the RX8 bit position in the
UCTRL3 register. The 9^th bit must be read from the RX8 bit before reading the low 8 bits from the
UDATA register. Likewise, the error flags FE, DOR, PE must be read before reading the data from
UDATA register. This is because the error flags are stored in the same FIFO position of the receive
buffer.
4.6.9.2 Receiver flag and interrupt
The USART Receiver has one flag that indicates the Receiver state.
The Receive Complete (RXC) flag indicates whether there are unread data present in the receive
buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty. If the Receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is
cleared.
When the Receive Complete Interrupt Enable (RXCIE) bit in the UCTRL2 register is set and Global
Interrupt is enabled, the USART Receiver Complete Interrupt is generated while RXC flag is set.
The USART Receiver has three error flags which are Frame Error (FE), Data OverRun (DOR) and
Parity Error (PE). These error flags can be read from the USTAT register. As data received are stored
in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer.
So, before reading received data from UDATA register, read the USTAT register first which contains
error flags.
The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is zero when the stop
bit was correctly detected as one, and the FE flag is one when the stop bit was incorrect, ie detected
as zero. This flag can be used for detecting out-of-sync conditions between data frames.
The Data OverRun (DOR) flag indicates data loss due to a receive buffer full condition. A DOR
occurs when the receive buffer is full, and another new data is present in the receive shift register
which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost.
To prevent data loss or clear this flag, read the receive buffer.
The Parity Error (PE) flag indicates that the frame in the receive buffer had a Parity Error when
received. If Parity Check function is not enabled (UPM[1]=0), the PE bit is always read zero.
Note) The error flags related to receive operation are not used when USART is in spi mode.
4.6.9.3 Parity Checker
If Parity Bit is enabled (UPM[1]=1), the Parity Checker calculates the parity of the data bits in
incoming frame and compares the result with the parity bit from the received serial frame.
PS029502-0212
PRELIMINARY
102