Z51F0410 Datasheet, PDF (101/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

4.6.3 Clock Generation
Z51F0410
Product Specification
SCLK
XCK
UBAUD
fSCLK
Prescaling
Up-Counter
(UBAUD+1)
/8
/2
Sync Register
Edge
Detector
UCPOL
/2
U2X
M
U
M
X
U
X
MASTER
txclk
M
UMSEL0
U
X
M
U
rxclk
X
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The Clock generation logic generates the base clock for the Transmitter and Receiver. The USART
supports four modes of clock operation and those are Normal Asynchronous, Double Speed
Asynchronous, Master Synchronous and Slave Synchronous. The clock generation scheme for
Master SPI and Slave SPI mode is the same as Master Synchronous and Slave Synchronous
operation mode. The UMSELn bit in UCTRL1 register selects between asynchronous and
synchronous operation. Asynchronous Double Speed mode is controlled by the U2X bit in the
UCTRL2 register. The MASTER bit in UCTRL2 register controls whether the clock source is internal
(Master mode, output port) or external (Slave mode, input port). The XCK pin is only active when the
USART operates in Synchronous or SPI mode.
Table below contains equations for calculating the baud rate (in bps).
Table 4.9 Equations for Calculating Baud Rate Register Setting
Operating Mode
Asynchronous Normal Mode (U2X=0)
Asynchronous Double Speed Mode (U2X=1)
Synchronous or SPI Master Mode
Equation for Calculating Baud Rate
Baud Rate
fSCLK
16 UBAUD 1
Baud Rate
fSCLK
8 UBAUD 1
Baud Rate
fSCLK
2 UBAUD 1
PS029502-0212
PRELIMINARY
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