Z51F0410 Datasheet, PDF (128/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
I2CSCLLR (SCL Low Period Register) : DCH
7
SCLL7
R/W
6
SCLL6
R/W
5
SCLL5
R/W
4
SCLL4
R/W
3
SCLL3
R/W
2
SCLL2
R/W
1
SCLL1
R/W
0
SCLL0
R/W
Initial value : 3FH
SCLL[7:0]
This register defines the LOW period of SCL when I2C operates in
master mode. The base clock is SCLK, the system clock, and the
period is calculated by the formula : tSCLK (SCLL + 1) where tSCLK
is the period of SCLK.
I2CSCLHR (SCL High Period Register) : DDH
7
SCLH7
R/W
6
SCLH6
R/W
5
SCLH5
R/W
4
SCLH4
R/W
3
SCLH3
R/W
2
SCLH2
R/W
1
SCLH1
R/W
0
SCLH0
R/W
Initial value : 3FH
SCLH[7:0]
This register defines the HIGH period of SCL when I2C operates in
master mode. The base clock is SCLK, the system clock, and the
period is calculated by the formula : tSCLK (SCLH + 3) where tSCLK
is the period of SCLK.
So, the operating frequency of I2C in master mode (fI2C) is calculated by the following equation.
fI2C
tSCLK
1
SCLL SCLH 4
I2CSDAHR (SDA Hold Time Register) : DEH
7
SDAH7
R/W
6
SDAH6
R/W
5
SDAH5
R/W
4
SDAH4
R/W
3
SDAH3
R/W
2
SDAH2
R/W
1
SDAH1
R/W
0
SDAH0
R/W
Initial value : 01H
SDAH[7:0]
This register is used to control SDA output timing from the falling
edge of SCL. Note that SDA is changed after tSCLK SDAH. In
master mode, load half the value of SCLL to this register to make
SDA change in the middle of SCL. In slave mode, configure this
register regarding the frequency of SCL from master. The SDA is
changed after tSCLK (SDAH + 1). So, to insure normal operation in
slave mode, the value tSCLK (SDAH + 1) must be smaller than the
period of SCL.
I2CDR (I2C Data Register) : DFH
7
6
5
4
3
2
1
0
ICD7
ICD6
ICD5
ICD4
ICD3
ICD2
ICD1
ICD0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : FFH
ICD[7:0]
When I2C is configured as a transmitter, load this register with data
to be transmitted. When I2C is a receiver, the received data is
stored into this register.
I2CSAR (I2C Slave Address Register) : D7H
7
6
5
4
3
2
1
0
PS029502-0212
PRELIMINARY
125