Z51F0410 Datasheet, PDF (107/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
BIT n
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
1
2
3
4
5
6
7
8
1
The process for detecting s^Ftⁱo^gp^urebi⁴t ^.2is^{3 S}lik^ae^mpc^lloⁱⁿc^gk^oa^f n^Dd^atd^aa^atⁿa^dr^Pe^ac^ro^itv^ye^Bry^it process. That is, if 2 or more
samples of 3 center values have high level, correct stop bit is detected, else a Frame Error flag is set.
After deciding first stop bit whether a valid stop bit is received or not, the Receiver goes idle state and
monitors the RXD line to check a valid high to low transition is detected (start bit detection).
RxD
STOP 1
(A)
(B)
(C)
Sample
(U2X = 0)
Sample
(U2X = 1)
1 2 3 4 5 6 7 8 9 10 11 12 13
1
2
3
4
5
6
7
4.6.10 SPI Mode
Figure 4.24 Stop Bit Sampling and Next Start Bit Sampling
The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the
following features.
- Full duplex, three-wire synchronous data transfer
- Master or Slave operation
- Supports all four SPI modes of operation (mode0, 1, 2, and 3)
- Selectable LSB first or MSB first data transfer
- Double buffered transmit and receive
- Programmable transmit bit rate
When SPI mode is enabled (UMSEL[1:0]=3), the Slave Select (SS) pin becomes active low input in
slave mode operation, or can be output in master mode operation if SPISS bit is set.
Note that during SPI mode of operation, the pin RXD is renamed as MISO and TXD is renamed as
MOSI for compatibility to other SPI devices.
4.6.10.1 SPI Clock formats and timing
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the
USART has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four
clock formats for data transfers. UCPOL selectively insert an inverter in series with the clock. UCPHA
chooses between two different clock phase relationships between the clock and data. Note that
PS029502-0212
PRELIMINARY
104