Z51F0410 Datasheet, PDF (126/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

Z51F0410
Product Specification
Figure 4.37 Formats and States in the Slave Receiver Mode
4.7.9 Register Map
Name
I2CMR
I2CSR
I2CSCLLR
I2CSCLHR
I2CSDAHR
I2CDR
I2CSAR
Address
DAH
DBH
DCH
DDH
DEH
DFH
D7H
Table 4.15 I2C Register Map
Dir
R/W
R
R/W
R/W
R/W
R/W
R/W
Default
00H
00H
3FH
3FH
01H
FFH
00H
Description
I2C Mode Control Register
I2C Status Register
SCL Low Period Register
SCL High Period Register
SDA Hold Time Register
I2C Data Register
I2C Slave Address Register
4.7.10 I2C Register description
I2C Registers are composed of I2C Mode Control Register (I2CMR), I2C Status Register (I2CSR),
SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time
Register (I2CSDAHR), I2C Data Register (I2CDR), and I2C Slave Address Register (I2CSAR).
4.7.11 Register description for I2C
I2CMR (I2C Mode Control Register) : DAH
7
6
5
4
3
2
1
0
IIF
IICEN
RESET
INTEN
ACKEN
IMASTERl
STOP
START
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value : 00H
IIF
IICEN
RESET
INTEN
ACKEN
MASTER
This is interrupt flag bit.
0
No interrupt is generated or interrupt is cleared
1
An interrupt is generated
Enable I2C Function Block (by providing clock)
0
I2C is inactive
1
I2C is active
Initialize internal registers of I2C.
0
No operation
1
Initialize I2C, auto cleared
Enable interrupt generation of I2C.
0
Disable interrupt, operates in polling mode
1
Enable interrupt
Controls ACK signal generation at ninth SCL period.
Note) ACK signal is output (SDA=0) for the following 3 cases.
When received address packet equals to SLA bits in I2CSAR
When received address packet equals to value 0x00 with GCALL
enabled
When I2C operates as a receiver (master or slave)
0
No ACK signal is generated (SDA=1)
1
ACK signal is generated (SDA=0)
This bit shows whether I2C is in master or slave mode.
PS029502-0212
PRELIMINARY
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