Z51F0410 Datasheet, PDF (29/184 Pages) Zilog, Inc. – Z8051 Series 8-Bit Microcontrollers

1.11.2 P0[1] Port Structure
Output
Input
Pull-up Enable
Open-Drain
Output Data
0
TXD ¹
TXD_OUT_EN
Direction
P0DA_OEB
P0RDA_OEB
Data
PAD DATA
Secondary
Input
Analog
Input
PCI_EN[1]
PCI_IN[1]
EXT_INT1
EXT_INT1_EN
TXD_IN_EN
RXD
AN1
AN1_EN
XOUT_EN (from Config)
XOUT(SUBXOUT)
Z51F0410
Product Specification
VDD
VDD
XOUT(SUBXOUT)
/ AN1 / INT1 /
TXD(RXD) / P01
1
0
LPF
NC20NS
Figure 1.19 XOUT(SUBXOUT) / AN1 / INT1 / TXD / P0[1] Port Structure
The Figure 1.19 shows a brief diagram of P0[1] port structure. The pull-up resister is directly
controlled by the pull-up register bit regardless of current port direction. The open-drain control is also
by open-drain register. On open-drain mode, the push-pull drives just N-MOS. When the direction is
output (value 1), the output PAD voltage is controlled by push-pull driver for the current output data.
The secondary input or analog channel selection bit disable the output direction regardless of the
current direction register. The secondary input INT1_EN, PCI_EN[1] enables the input data path
continuously. On normal read mode (non secondary mode), the input data path is only enabled during
the CPU OEB (active low). When the analog channel (AN1) is enabled, the first input gate from the
PAD is disabled (highest priority) to prevent the input leakage current for the floating voltage status.
The XOUT function disables all analog channels and secondary input/output. At read operation, the
input data is selected by PAD direction register. If its value is ‘1’, it reads the current output register
value. Otherwise, it reads the current PAD voltage directly (just during OEB active). In addition,
always the current PAD voltage is read by PAD DATA register.
PS029502-0212
PRELIMINARY
26