SMJ320F240 Datasheet, PDF (93/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
register file compilation (continued)
Table 18. Register File Compilation (Continued)
SGUS029 – APRIL 1999
ADDR
BIT 15
BIT 7
07050h
07051h
07052h
07053h
STOP
BITS
—
BAUD15
(MSB)
BAUD7
07054h TXRDY
07055h
07056h
07057h
07058h
07059h
0705Ah
to
0705Dh
0705Eh
RX ERROR
ERXDT7
RXDT7
TXDT7
SCITXD
DATA IN
0705Fh
—
07060h
to
0706Fh
07070h
07071h
07072h
07073h
to
07077h
07078h
07079h
XINT1
FLAG
—
NMI
FLAG
—
XINT2
FLAG
—
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
SERIAL COMMUNICATIONS INTERFACE (SCI) CONFIGURATION CONTROL REGISTERS
EVEN/ODD
PARITY
PARITY
ENABLE
SCI ENA
ADDR/IDLE
MODE
SCI
CHAR2
SCI
CHAR1
RX ERR
INT ENA
SW RESET CLOCK ENA TXWAKE
SLEEP
TXENA
BAUD14
BAUD13
BAUD12
BAUD11
BAUD10
BAUD9
BAUD6
TX EMPTY
RXRDY
ERXDT6
RXDT6
BAUD5
—
BRKDT
ERXDT5
RXDT5
TXDT6
TXDT5
BAUD4
BAUD3
—
—
FE
OE
ERXDT4
ERXDT3
RXDT4
RXDT3
Reserved
TXDT4
TXDT3
BAUD2
—
PE
ERXDT2
RXDT2
TXDT2
BAUD1
RX/BK
INT ENA
RXWAKE
ERXDT1
RXDT1
TXDT1
Reserved
SCITXD
DATA OUT
SCITX
PRIORITY
SCITXD
FUNCTION
SCIRX
PRIORITY
SCITXD
DATA DIR
SCI
ESPEN
SCIRXD
DATA IN
—
SCIRXD
DATA OUT
—
SCIRXD
FUNCTION
—
Reserved
—
XINT1
PIN DATA
—
NMI
PIN DATA
EXTERNAL INTERRUPT CONTROL REGISTERS
—
—
—
—
0
—
—
XINT1
POLARITY
Reserved
—
—
—
—
1
—
—
NMI
POLARITY
—
XINT1
PRIORITY
—
—
Reserved
—
—
—
—
—
—
XINT2
PIN DATA
—
XINT2
DATA DIR
XINT2
DATA OUT
XINT2
POLARITY
XINT2
PRIORITY
Reserved
BIT 8
BIT 0
SCI
CHAR0
RXENA
BAUD8
BAUD0
(LSB)
TX
INT ENA
—
ERXDT0
RXDT0
TXDT0
SCIRXD
DATA DIR
—
—
XINT1
ENA
—
—
—
XINT2
ENA
REG
SCICCR
SCICTL1
SCIHBAUD
SCILBAUD
SCICTL2
SCIRXST
SCIRXEMU
SCIRXBUF
SCITXBUF
SCIPC2
SCIPRI
XINT1CR
NMICR
XINT2CR
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