SMJ320F240 Datasheet, PDF (11/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
device memory map
The SMJ320F240 implements three separate address spaces for program memory, data memory, and I / O.
Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to
32K words at the top of the address range can be defined to be external global memory in increments of powers
of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory
is arbitrated using the global memory bus request (BR) signal.
On the ’F240, the first 96 (0 – 5Fh) data memory locations are either allocated for memory-mapped registers
or are reserved. This memory-mapped register space contains various control and status registers including
those for the CPU.
All the on-chip peripherals of the ’F240 device are mapped into data memory space. Access to these registers
is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map.
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