SMJ320F240 Datasheet, PDF (30/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
functional block diagram of the SMJ320F240 DSP CPU
Program Bus
A15–A0
D15–D0
IS
DS
PS
R/W
STRB
READY
BR
XF
RS
MP/MC
XINT[1–3]
3
16
X1
CLKOUT1
CLKIN/X2
16
PC
W/R
WE
NMI
MUX
NPAR
PAR MSTACK
MUX
Stack 8 × 16
FLASH EEPROM
16
16
16
Program Control
(PCTRL)
16
16
16
16
3
ARP(3)
3
3
ARB(3)
3
16
16
16
AR0(16)
AR1(16)
AR2(16)
AR3(16)
AR4(16)
AR5(16)
AR6(16)
AR7(16)
9
DP(9)
9
16
16 _{Memory Map}
Register
IMR (16)
IFR (16)
GREG (16)
16
ARAU(16)
MUX
MUX
Data/Prog
DARAM
B0 (256 × 16)
MUX
16
MUX
Data
DARAM
B2 (32 × 16)
B1 (256 × 16)
16
Data Bus
16
7
16
LSB
from
IR
16
MUX
16 16
MUX
16
TREG0(16)
Multiplier
ISCALE (0–16)
PREG(32)
32
PSCALE (–6, 0, 1, 4)
32
32
MUX
32
CALU(32)
32
32
C ACCH(16) ACCL(16)
32
OSCALE (0–7)
16
16
NOTES: A. Symbol descriptions appear in Table 10.
B. For clarity the data and program buses are shown as single buses although they include address and data bits.
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