SMJ320F240 Datasheet, PDF (18/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
reset (continued)
The occurrence of a reset condition causes the SMJ320F240 to terminate program execution and affects
various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are
affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers
are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct
operation.
After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag
(ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag
(WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags.
RS and PORESET must be held low until the clock signal is valid and V_CC is within the operating range. In
addition, PORESET must be driven low when V_CC drops below the minimum operating voltage.
hardware-generated interrupts
All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When
more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets
acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable
interrupt lines (INT1–INT6) and one is for the nonmaskable interrupt (NMI) line. INT1–INT6 and NMI have the
priorities shown in Table 5.
Table 5. Interrupt Priorities at the Level of the DSP Core
INTERRUPT
PRIORITY AT THE
DSP CORE
RESET
1
TI RESERVED†
2
NMI
3
INT1
4
INT2
5
INT3
6
INT4
7
INT5
8
INT6
9
TI RESERVED†
10
† _{TI Reserved means that the address space is}
reserved for Texas Instruments.
The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6
and shown in Figure 5.
Table 6. Interrupt Lines Controlled by the System Module and Event Manager
PERIPHERAL
System Module
Event Manager
INTERRUPT LINES
INT1
INT5
NMI
INT6
INT2
INT3
INT4
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