SMJ320F240 Datasheet, PDF (13/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
peripheral memory map
The SMJ320F240 system and peripheral control register frame contains all the data, status, and control bits
to operate the system and peripheral modules on the device (excluding the event manager).
Reserved
Interrupt-Mask Register
Hex
0000
0003
0004
Hex
0000
005F
0060
007F
0080
Memory-Mapped Registers
and Reserved
On-Chip DARAM B2
Global-Memory Allocation
Register
Interrupt Flag Register
Emulation Registers
and Reserved
0005
0006
0007
005F
01FF
0200
02FF
0300
03FF
0400
07FF
0800
6FFF
7000
73FF
7400
743F
7440
77FF
7800
7FFF
8000
FFFF
Reserved
On-Chip DARAM
B0 (CNF = 0)
Reserved (CNF = 1)
On-Chip
DARAM B1
Reserved
Illegal
Peripheral Frame 1
Peripheral Frame 2
Reserved
Illegal
External
Illegal
System Configuration and
Control Registers
Watchdog Timer and
PLL Control Registers
ADC
SPI
SCI
Illegal
External-Interrupt Registers
Illegal
Digital-I/O Control Registers
Illegal
General-Purpose
Timer Registers
Reserved
Compare, PWM, and
Deadband Registers
Reserved
Capture & QEP Registers
Reserved
Interrupt Mask, Vector and
Flag Registers
Reserved
Figure 2. Peripheral Memory Map
7000 – 700F
7010 – 701F
7020 – 702F
7030 – 703F
7040 – 704F
7050 – 705F
7060 – 706F
7070 – 707F
7080 – 708F
7090 – 709F
70A0 – 73FF
7400 – 740C
740D – 7410
7411 – 741C
741D – 741F
7420 – 7426
7427 – 742B
742C – 7434
7435 – 743F
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