SMJ320F240 Datasheet, PDF (16/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
group2 shared I/O pins
Group2 shared pins belong to peripherals that have built-in general-purpose I/O capability. Control and
configuration for these pins are achieved by setting the appropriate bits within the control and configuration
registers of the peripherals. Table 3 lists the Group2 shared pins.
Table 3. Group2 Shared Pin Configurations
PIN #
43
44
45
48
49
51
54
55
PRIMARY FUNCTION
SCIRXD
SCITXD
SPISIMO
SPISOMI
SPICLK
SPISTE
XINT2
XINT3
REGISTER
SCIPC2
SCIPC2
SPIPC2
SPIPC2
SPIPC1
SPIPC1
XINT2CR
XINT3CR
ADDRESS
705Eh
705Eh
704Eh
704Eh
704Dh
704Dh
7078h
707Ah
PERIPHERAL MODULE
SCI
SCI
SPI
SPI
SPI
SPI
External Interrupts
External Interrupts
digital I/O control registers
Table 4 lists the registers available to the digital I/O module. As with other ’F240 peripherals, the registers are
memory-mapped to the data space.
ADDRESS
7090h
7092h
7098h
709Ah
709Ch
Table 4. Addresses of Digital I/O Control Registers
REGISTER
OCRA
OCRB
PADATDIR
PBDATDIR
PCDATDIR
NAME
I/O mux control register A
I/O mux control register B
I/O port A data and direction register
I/O port B data and direction register
I/O port C data and direction register
device reset and interrupts
The SMJ320F240 software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The ’F240 recognizes three types of
interrupt sources:
D Reset (hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
D Hardware-generated interrupts are requested by external pins or by on-chip peripherals. There are two
types:
– External interrupts are generated by one of five external pins corresponding to the interrupts XINT1,
XINT2, XINT3, PDPINT, and NMI. The first four can be masked both by dedicated enable bits and by the
CPU’s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core. NMI,
which is not maskable, takes priority over peripheral interrupts and software-generated interrupts. It can
be locked out only by an already executing NMI or a reset.
– Peripheral interrupts are initiated internally by these on-chip peripheral modules: the event manager,
SPI, SCI, watchdog / real-time interrupt (WD/RTI), and ADC. They can be masked both by enable bits
for each event in each peripheral and by the CPU’s IMR, which can mask each maskable interrupt line at
the DSP core.
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