SMJ320F240 Datasheet, PDF (37/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
flash control mode register (continued)
not available. Switching between the register access mode and the array access mode is done by issuing the
IN and OUT instructions. The memory content in these instructions (denoted by xxxx) is not relevant. See the
TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282) for a
detailed description of the flash programming algorithms.
peripherals
The integrated peripherals of the SMJ320F240 are described in the following subsections:
D External memory interface
D Event manager (EV)
D Dual analog-to-digital converter (ADC)
D Serial peripheral interface (SPI)
D Serial communications interface (SCI)
D Watchdog timer (WD)
external memory interface
The SMJ320F240 can address up to 64K words × 16 bits of memory or registers in each of the program, data,
and I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high
32K words can be mapped dynamically as either local or global using the GREG register. A data-memory
access mapped as global asserts BR low (with timing similar to the address bus).
The CPU of the SMJ320F240 schedules a program fetch, data read, and data write on the same machine cycle.
This is because, from on-chip memory, the CPU can execute all three of these operations in the same cycle.
However, the external interface multiplexes the internal buses to one address and one data bus. The external
interface sequences these operations to complete the data write first, then the data read, and finally the program
read.
The ’F240 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces
provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along
with the PS, DS, and IS space-select signals allow addressing of 64K 16-bit words in program and I/O space.
Due to the on-chip peripherals, external data space is addressable to 32K 16-bit words.
I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O
address space using the processor’s external address and data buses in the same manner as memory-mapped
devices.
The ’F240 external parallel interface provides control signals to facilitate interfacing to the device. The R/W
output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal
provides a timing reference for all external cycles.
Interface to memory and I/O devices of varying speeds is accomplished by using the READY input. When
transactions are made with slower devices, the ’F240 processor waits until the other device completes its
function and signals the processor by way of the READY input. Once a ready indication is provided from the
external device, execution continues. On the ’F240 device, the READY input must be driven (active high) to
complete reads or writes to internal data I/O-memory-mapped registers and all external addresses.
The bus request (BR) signal is used in conjunction with the other ’F240 interface signals to arbitrate external
global-memory accesses. Global memory is external data-memory space in which the BR signal is asserted
at the beginning of the access. When an external global-memory device receives the bus request, it responds
by asserting the ready signal after the global-memory access is arbitrated and the global access is completed.
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