SMJ320F240 Datasheet, PDF (4/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
Terminal Functions
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
EXTERNAL INTERFACE DATA/ADDRESS SIGNALS
A0 (LSB)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15 (MSB)
110
111
112
114
115
116
117
Parallel address bus A0 [least significant bit (LSB)] through A15 [most significant bit (MSB)]. A15 – A0
118
119
O/Z
are multiplexed to address external data/program memory or I/O. A15 – A0 are placed in the
high-impedance state when EMU1/OFF is active low and hold their previous states in power-down
122
modes.
123
124
125
126
127
128
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15 (MSB)
9
10
11
12
15
16
17
Parallel data bus D0 (LSB) through D15 (MSB). D15 – D0 are multiplexed to transfer data between the
18
19
I/O/Z
SMJ320F240 and external data/program memory and I/O space (devices). D15 – D0 are placed in the
high-impedance state when not outputting, when in power-down mode, when reset (RS) is asserted, or
22
when EMU1/OFF is active low.
23
24
25
26
27
28
EXTERNAL INTERFACE CONTROL SIGNALS
DS
129
Data, program, and I/O space select signals. DS, PS, and IS are always high unless low-level asserted
PS
131
O/Z for communication to a particular external space. They are placed in the high-impedance state during
IS
130
reset, power down, and when EMU1/OFF is active low.
READY
36
I
Data ready. READY indicates that an external device is prepared for the bus transaction to be completed.
If the device is not ready (READY is low), the processor waits one cycle and checks READY again.
Read/write signal. R/W indicates transfer direction during communication to an external device. It is
R/W
4
O/Z normally in read mode (high), unless low level is asserted for performing a write operation. It is placed
in the high-impedance state during reset, power down, and when EMU1/OFF is active low.
STRB
Strobe. STRB is always high unless asserted low to indicate an external bus cycle. It is placed in the
6
O/Z _{high-impedance state during reset, power down, and when EMU1/OFF is active low.}
Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15 – D0).
WE
1
O/Z
Data can be latched by an external device on the rising edge of WE. WE is active on all external program,
data, and I/O writes. WE goes in the high-impedance state following reset and when EMU1/OFF is active
low.
W/R
132
O/Z
Write/read. W / R is an inverted form of R/W and can connect directly to the output enable of external
devices. W/R is placed in the high-impedance state following reset and when EMU1/OFF is active low.
† _{I = input, O = output, Z = high impedance}
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