SMJ320F240 Datasheet, PDF (91/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
register file compilation
Table 18 is a collection of all the programmable registers of the SMJ320F240 (provided for a quick reference).
Table 18. Register File Compilation
ADDR
BIT 15
BIT 7
DP(7)
1
—
00004h
—
—
00005h
—
00006h
—
07018h
07019h
0701Ah
0701Bh
to
0701Dh
0701Eh
0701Fh
RESET1
CLKSRC1
PORST
—
0
D7
07020h
07021h
07022h
07023h
07024h
07025h
07026h
07027h
07028h
07029h
D7
D7
D7
RTI FLAG
WD FLAG
0702Ah
0702Bh
0702Ch
CLKMD(1)
BIT 14
BIT 6
ARP
DP(6)
ARB
1
—
—
—
—
—
RESET0
CLKSRC0
—
—
BIT 13
BIT 12
BIT 11
BIT 10
BIT 5
BIT 4
BIT 3
BIT 2
DATA MEMORY SPACE
CPU STATUS REGISTERS
OV
OVM
1
DP(5)
DP(4)
DP(3)
DP(2)
CNF
TC
SXM
1
XF
1
1
GLOBAL MEMORY AND CPU INTERRUPT REGISTERS
—
—
—
—
INT6 MASK INT5 MASK INT4 MASK INT3 MASK
—
—
—
—
Global Data Memory Configuration Bits (7–0)
—
—
—
—
INT6 FLAG INT5 FLAG INT4 FLAG INT3 FLAG
SYSTEM CONFIGURATION REGISTERS
—
—
—
—
—
—
—
—
Reserved
—
ILLADR
—
SWRST
HPO
—
VCCAOR
—
BIT 9
BIT 1
BIT 8
BIT 0
INTM
DP(1)
C
DP(8)
DP(0)
1
PM
—
INT2 MASK
—
—
INT1 MASK
—
—
INT2 FLAG
—
INT1 FLAG
—
—
—
—
WDRST
—
—
VECRD
REG
ST0
ST1
IMR
GREG
IFR
SYSCR
SYSSR
Reserved
0
D6
D6
D6
D6
RTI ENA
WDDIS
CLKMD(0)
0
0
0
0
D5
D4
D3
D2
Reserved
WD/RTI CONTROL REGISTERS
Reserved
D5
D4
D3
D2
Reserved
D5
D4
D3
D2
Reserved
D5
D4
D3
D2
Reserved
—
—
—
RTIPS2
Reserved
WDCHK2
WDCHK1
WDCHK0
WDPS2
PLL CLOCK CONTROL REGISTERS
Reserved
PLLOCK(1) PLLOCK(0) PLLPM(1)
PLLPM(0)
Reserved
0
D1
D1
D1
D1
RTIPS1
WDPS1
ACLKENA
0
SYSIVR
D0
D0
D0
D0
RTIPS0
WDPS0
RTICNTR
WDCNTR
WDKEY
RTICR
WDCR
PLLPS
CKCR0
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
91