SMJ320F240 Datasheet, PDF (2/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Terminal Functions Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device Reset and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functional Block Diagram of the CPU . . . . . . . . . . . . . . . . . . . 30
DSP Core CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Scan-based Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SMJ320F240 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . 57
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Signal Transition Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Memory and Peripheral Interface Timing . . . . . . . . . . . . . . . . . 66
I/O Timing Variation: SPICE Simulation Results . . . . . . . . . . . 70
READY Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RS and PORESET Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
XF, BIO, and MP/MC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Timing Event Manager Interface . . . . . . . . . . . . . . . . . . . . . . . . 75
PWM/CMP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Capture and QEP Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
General-Purpose Input/Output Timings . . . . . . . . . . . . . . . . . . 77
Serial Communications Interface (SCI) I/O Timings . . . . . . . . 78
Timing Characteristics for SCI . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI Master Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . 79
SPI Slave Mode Timing Parameters . . . . . . . . . . . . . . . . . . . . . 83
10-Bit Dual Analog-to-Digital Converter (ADC) . . . . . . . . . . . . 87
ADC Input Pin Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
ADC Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Programming Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Flash-write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Register File Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
description (continued)
Table 1. Characteristics of the ’F240 DSP Controller
DEVICE
SMJ320F240
ON-CHIP MEMORY (WORDS)
RAM
FLASH
EEPROM
DATA
DATA / PROG
PROG
288
256
16K
POWER
SUPPLY
(V)
5
CYCLE
TIME
(ns)
50
PACKAGE
TYPE
PIN COUNT
HFP 132–P
The functional block diagram provides a high-level description of each component in the ’F240 DSP controller.
The SMJ320F240 device is composed of three main functional units: a ’C2xx DSP core, internal memory, and
peripherals. In addition to these three functional units, there are several system-level features of the ’F240 that
are distributed. These system features include the memory map, device reset, interrupts, digital input / output
(I / O), clock generation, and low-power operation.
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