SMJ320F240 Datasheet, PDF (53/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
instruction set summary (continued)
Table 14. SMJ320F240 Instruction Set Summary (Continued)
’F240
MNEMONIC
DESCRIPTION
WORDS/
CYCLES _MSB
OPCODE
LSB
Branch if accumulator ≠ 0
2/4/2
1110 0011 0000 1000
Branch Address
BCND
Branch on overflow
2/4/2
1110 0011 0010 0010
Branch Address
Branch if accumulator = 0
2/4/2
1110 0011 1000 1000
Branch Address
BIT
Test bit
1/1
0100 BITx IADD RESS
BITT
Test bit specified by TREG
1/1
0110 1111 IADD RESS
BLDD†
Block move from data memory to data memory source immediate
Block move from data memory to data memory destination immediate
1010 1000 IADD RESS
2/3
Branch Address
1010 1001 IADD RESS
2/3
Branch Address
BLPD
Block move from program memory to data memory
1010 0101 IADD RESS
2/3
Branch Address
CALA
Call subroutine indirect
1/4
1011 1110 0011 0000
CALL
Call subroutine
0111 1010 IADD RESS
2/4
Routine Address
CC
Conditional call subroutine
2/4/2
1110 10TP ZLVC ZLVC
Routine Address
Configure block as data memory
1/1
1011 1110 0100 0100
Enable interrupt
1/1
1011 1110 0100 0000
Reset carry bit
1/1
1011 1110 0100 1110
CLRC
Reset overflow mode
1/1
1011 1110 0100 0010
Reset sign-extension mode
1/1
1011 1110 0100 0110
Reset test / control flag
1/1
1011 1110 0100 1010
Reset external flag
1/1
1011 1110 0100 1100
CMPL
Complement accumulator
1/1
1011 1110 0000 0001
CMPR
Compare auxiliary register with auxiliary register AR0
1/1
1011 1111 0100 01CM
DMOV
Data move in data memory
1/1
0111 0111 IADD RESS
IDLE
Idle until interrupt
1/1
1011 1110 0010 0010
IN
Input data from port
1010 1111 IADD RESS
2/2
16BIT I / O PORT ADRS
INTR
Software-interrupt
1/4
1011 1110 011K KKKK
Load accumulator with shift
1/1
0001 SHFT IADD RESS
LACC
Load accumulator long immediate with shift
1011 1111 1000 SHFT
2/2
16-Bit Constant
Zero low accumulator and load high accumulator
1/1
0110 1010 IADD RESS
† _{In ’F240 devices, the BLDD instruction does not work with memory-mapped registers IMR, IFR, and GREG.}
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