SMJ320F240 Datasheet, PDF (64/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
timing requirements (see Note 3 and Figure 21)
EXTERNAL REFERENCE
CRYSTAL
MIN MAX UNIT
4 MHz
250
†
tc(Cl)
Cycle time, XTAL1/CLKIN
6 MHz
8 MHz
167
ns
125
tf(Cl)
Fall time, XTAL1/CLKIN
5 ns
tr(Cl)
Rise time, XTAL1/CLKIN
5 ns
tw(CIL)
Pulse duration, XTAL1/CLKIN low as a percentage of tc(CI)
40
60 %
tw(CIH)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(CI)
40
60 %
† _{This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is}
characterized at frequencies approaching 0 Hz.
NOTE 3: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
XTAL1/CLKIN
tw(CIH)
tc(CI)
tf(Cl)
tw(CIL)
tr(Cl)
tc(CO)
tw(COH)
tw(COL)
tr(CO)
tf(CO)
CLKOUT
Figure 21. CLKIN-to-CLKOUT Timings for PLL Oscillator Mode, Multiply-by-5 Option With 4-MHz Crystal
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