SMJ320F240 Datasheet, PDF (92/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
register file compilation (continued)
Table 18. Register File Compilation (Continued)
ADDR
0702Dh
0702Eh
to
07031h
07032h
07033h
07034h
07035h
07036h
07037h
07038h
07039h
to
0703Fh
07040h
07041h
07042h
07043h
07044h
07045h
07046h
07047h
07048h
07049h
0704Ah
to
0704Ch
0704Dh
0704Eh
0704Fh
BIT 15
BIT 7
CKINF(3)
BIT 14
BIT 6
CKINF(2)
BIT 13
BIT 12
BIT 11
BIT 10
BIT 5
BIT 4
BIT 3
BIT 2
PLL CLOCK CONTROL REGISTERS (CONTINUED)
CKINF(1)
CKINF(0)
PLLDIV(2)
PLLFB(2)
BIT 9
BIT 1
PLLFB(1)
BIT 8
BIT 0
PLLFB(0)
Reserved
SUSPEND-
SOFT
ADCEOC
SUSPEND-
FREE
—
—
ADCFIFO1
D9
D8
D1
D0
D9
D8
D1
D0
A-to-D MODULE CONTROL REGISTERS
ADCIM-
START
ADC1EN
ADC2EN
ADCCON-
RUN
ADC2CHSEL
ADC1CHSEL
Reserved
—
—
—
ADCEVSOC
—
ADCFIFO2
Reserved
D7
D6
D5
D4
0
0
0
0
Reserved
D7
D6
D5
D4
0
0
0
0
ADCINTEN
ADCEXTSOC
ADCPSCALE
D3
0
D3
0
ADCINTFLAG
ADCSOC
—
D2
0
D2
0
Reserved
SPI SW
RESET
—
RECEIVER
OVERRUN
—
ERCVD7
RCVD7
SDAT7
SERIAL PERIPHERAL INTERFACE (SPI) CONFIGURATION CONTROL REGISTERS
CLOCK
—
—
—
SPI
SPI
POLARITY
CHAR2
CHAR1
—
—
OVERRUN
INT ENA
CLOCK
PHASE
MASTER/
SLAVE
TALK
SPI INT
FLAG
—
—
—
—
—
Reserved
SPI BIT
RATE 6
SPI BIT
RATE 5
SPI BIT
RATE 4
SPI BIT
RATE 3
SPI BIT
RATE 2
SPI BIT
RATE 1
Reserved
ERCVD6
ERCVD5
ERCVD4
ERCVD3
ERCVD2
ERCVD1
RCVD6
RCVD5
RCVD4
RCVD3
RCVD2
RCVD1
Reserved
SDAT6
SDAT5
SDAT4
SDAT3
SDAT2
SDAT1
SPI
CHAR0
SPI INT
ENA
—
SPI BIT
RATE 0
ERCVD0
RCVD0
SDAT0
Reserved
SPISTE
DATA IN
SPISIMO
DATA IN
—
SPISTE
DATA OUT
SPISIMO
DATA OUT
SPI
PRIORITY
SPISTE
FUNCTION
SPISIMO
FUNCTION
SPI
ESPEN
SPISTE
DATA DIR
SPISIMO
DATA DIR
—
SPICLK
DATA IN
SPISOMI
DATA IN
—
SPICLK
DATA OUT
SPISOMI
DATA OUT
—
SPICLK
FUNCTION
SPISOMI
FUNCTION
—
SPICLK
DATA DIR
SPISOMI
DATA DIR
—
REG
CKCR1
ADCTRL1
ADCTRL2
ADCFIFO1
ADCFIFO2
SPICCR
SPICTL
SPISTS
SPIBRR
SPIEMU
SPIBUF
SPIDAT
SPIPC1
SPIPC2
SPIPRI
92
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