SMJ320F240 Datasheet, PDF (50/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
repeat feature (continued)
The repeat counter (RPTC) is loaded with the addressed data-memory location if direct or indirect addressing
is used, and with an 8-bit immediate value if short-immediate addressing is used. The RPTC register is loaded
by the RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared
by reset. Once a repeat instruction (RPT ) is decoded, all interrupts, including NMI (but excluding reset), are
masked until the completion of the repeat loop.
instruction set summary
This section summarizes the operation codes (opcodes) of the instruction set for the ’F240 digital signal
processors. This instruction set is a superset of the ’C1x and ’C2x instruction sets. The instructions are arranged
according to function and are alphabetized by mnemonic within each category. The symbols in Table 13 are
used in the instruction set summary table (Table 14). T he TI ’C2xx assembler accepts ’C2x instructions.
The number of words that an instruction occupies in program memory is specified in column 3 of Table 14.
Several instructions specify two values separated by a slash mark ( / ) for the number of words. In these cases,
different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies
one word when the operand is a short-immediate value or two words if the operand is a long-immediate value.
The number of cycles that an instruction requires to execute is also in column 3 of Table 14. All instructions are
assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The
cycle timings are for single-instruction execution, not for repeat mode.
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