SMJ320F240 Datasheet, PDF (5/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
Terminal Functions (Continued)
SGUS029 – APRIL 1999
TERMINAL
NAME
NO.
TYPE†
DESCRIPTION
EXTERNAL INTERFACE CONTROL SIGNALS (CONTINUED)
Bus request. BR is asserted during access of external global data memory space. BR can be used
BR
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O/Z to extend the data memory address space by up to 32K words. BR goes in the high-impedance
state during reset, power down, and when EMU1/OFF is active low.
VCCP/WDDIS
Flash-programming voltage supply. If VCCP = 5 V, then WRITE/ERASE can be made to the
ENTIRE on-chip flash memory block—that is, for programming the flash. If VCCP = 0 V, then
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WRITE/ERASE of the flash memory is not allowed, thereby protecting the entire memory block
from being overwritten. WDDIS also functions as a hardware watchdog disable. The watchdog
timer is disabled when VCCP/WDDIS = 5 V and bit 6 in WDCR is set to 1.
ADC INPUTS (UNSHARED)
ADCIN2
74
I
ADCIN3
75
I
ADCIN4
ADCIN5
76
I
Analog inputs to the first ADC
77
I
ADCIN6
78
I
ADCIN7
79
I
ADCIN10
89
I
ADCIN11
88
I
ADCIN12
ADCIN13
83
I
Analog inputs to the second ADC
82
I
ADCIN14
81
I
ADCIN15
80
I
BIT I/O AND SHARED FUNCTIONS PINS
ADCIN0/IOPA0
Bidirectional digital I/O.
72
I/O Analog input to the first ADC.
ADCIN0/IOPA0 is configured as a digital input by all device resets.
ADCIN1/IOPA1
Bidirectional digital I/O.
73
I/O Analog input to the first ADC.
ADCIN1/IOPA1 is configured as a digital input by all device resets.
ADCIN9/IOPA2
Bidirectional digital I/O.
90
I/O Analog input to the second ADC.
ADCIN9/IOPA2 is configured as a digital input by all device resets.
ADCIN8/IOPA3
Bidirectional digital I/O.
91
I/O Analog input to the second ADC.
ADCIN8/IOPA3 is configured as a digital input by all device resets.
PWM7/CMP7/IOPB0 100
I/O/Z
Bidirectional digital I/O. Simple compare/PWM 1 output. The state of PWM7/CMP7/IOPB0 is de-
termined by the simple compare/PWM and the simple action control register (SACTR). It goes to
the high-impedance state when unmasked PDPINT goes active low.
PWM7/CMP7/IOPB0 is configured as a digital input by all device resets.
PWM8/CMP8/IOPB1 101
I/O/Z
Bidirectional digital I/O. Simple compare/PWM 2 output. The state of PWM8/CMP8/IOPB1 is de-
termined by the simple compare/PWM and the SACTR. It goes to the high-impedance state when
unmasked PDPINT goes active low. PWM8/CMP8/IOPB1 is configured as a digital input by all
device resets.
PWM9/CMP9/IOPB2 102
I/O/Z
† _{I = input, O = output, Z = high impedance}
Bidirectional digital I/O. Simple compare/PWM 3 output. The state of PWM9/CMP9/IOPB2 is de-
termined by the simple compare/PWM and SACTR. It goes to the high-impedance state when un-
masked PDPINT goes active low. PWM9/CMP9/IOPB2 is configured as a digital input by all de-
vice resets.
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