SMJ320F240 Datasheet, PDF (44/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
serial peripheral Interface (SPI) module (continued)
SPIBUF.7 – 0
SPIBUF
Buffer Register
8
RECEIVER
OVERRUN
SPISTS.7
OVERRUN
INT ENA
SPICTL.4
SPI INT FLAG
SPISTS.6
SPI INT
ENA
SPICTL.0
To CPU
SPI Priority
SPIPRI.6
0 _{Level 1}
INT
1 _{Level 6}
INT
External
Connections
SPIDAT
Data Register
SPIDAT.7 – 0
TALK
SPICTL.1
State Control
SPI CHAR
SPICCR.2 – 0
210
SPI BIT RATE
SYSCLK
SPIBRR.6 – 0
6543210
M
S
SW1
M
S
SW2
M
S
M
S
SPIPC1.5
SPISTE
FUNCTION‡
MASTER/SLAVE†
SPICTL.2
S
SW3
CLOCK
CLOCK
M
S
POLARITY
PHASE
SPICCR.6
SPICTL.3
M
SPIPC2.7 – 4
SPISIMO
SPIPC2.3 – 0
SPISOMI
SPIPC1.7 – 4
SPISTE
SPIPC1.3 – 0
SPICLK
† _{The diagram is shown in the slave mode.}
‡ _{The SPISTE pin is shown as being disabled, meaning that data cannot be transmitted in this mode. Note that SW1, SW2, and SW3 are closed}
in this configuration.
Figure 13. Four-Pin Serial Peripheral Interface Module Block Diagram^†
44
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443