SMJ320F240 Datasheet, PDF (28/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
low-power modes (continued)
Table 10. Legend for the ’F240 Internal Hardware Functional Block Diagram
SYMBOL
ACC
ARAU
AUX
REGS
BR
C
CALU
DARAM
DP
GREG
IMR
IFR
INT#
ISCALE
MPY
MSTACK
MUX
NPAR
OSCALE
PAR
PC
PCTRL
NAME
DESCRIPTION
Accumulator
32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities
Auxiliary Register An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
Arithmetic Unit
and outputs
Auxiliary Registers
0–7
These 16-bit registers are used as pointers to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the auxiliary register pointer (ARP). AR0 can also be used
as an index value for AR updates of more than one and as a compare value to AR.
Bus Request
Signal
BR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available for the bus transaction. BR can be used to extend the data memory
address space by up to 32K words.
Carry
Register carry output from CALU. C is fed back into the CALU for extended arithmetic operation. The C bit
resides in status register 1 (ST1), and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.
Central Arithmetic
Logic Unit
32-bit-wide main arithmetic logic unit for the SMJ320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC, and
provides status results to PCTRL.
Dual Access RAM
If the on-chip RAM configuration control bit (CNF) is set to 0, the reconfigurable data dual-access RAM
(DARAM) block B0 is mapped to data space; otherwise, B0 is mapped to program space. Blocks B1 and B2
are mapped to data memory space only, at addresses 0300–03FF and 0060–007F, respectively. Blocks 0
and 1 contain 256 words, while Block 2 contains 32 words.
Data Memory
Page Pointer
The 9-bit DP register is concatenated with the seven LSBs of an instruction word to form a direct memory
address of 16 bits. DP can be modified by the LST and LDP instructions.
Global Memory
Allocation
Register
GREG specifies the size of the global data memory space.
Interrupt Mask
Register
IMR individually masks or enables the seven interrupts.
Interrupt Flag
Register
The 7-bit IFR indicates that the SMJ320C2xx has latched an interrupt from one of the seven maskable
interrupts.
Interrupt Traps
A total of 32 interrupts by way of hardware and/or software are available.
Input Data-Scaling 16 to 32-bit barrel left-shifter. ISCALE shifts incoming 16-bit data 0 to16 positions left, relative to the 32-bit
Shifter
output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
Multiplier
16 × 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
Micro Stack
MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.
Multiplexer
Multiplexes buses to a common input
Next Program
Address Register
NPAR holds the program address to be driven out on the PAB on the next cycle.
Output
Data-Scaling
Shifter
16 to 32-bit barrel left-shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the Data-Write Data
Bus (DWEB).
Program Address PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
Register
operations scheduled for the current bus cycle.
Program Counter
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
Program
Controller
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
28
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443