SMJ320F240 Datasheet, PDF (51/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
instruction set summary (continued)
SGUS029 – APRIL 1999
SYMBOL
A
ACC
ACCB
ARx
BITx
BMAR
DBMR
I
II...II
INTM
INTR#
K
PREG
PROG
RPTC
SHF, SHFT
TC
TP
TREGn
ZLVC
Table 13. SMJ320F240 Opcode Symbols
DESCRIPTION
Address
Accumulator
Accumulator buffer
Auxiliary register value (0 – 7)
4-bit field that specifies which bit to test for the BIT instruction
Block-move address register
Dynamic bit-manipulation register
Addressing-mode bit
Immediate operand value
Interrupt-mode flag bit
Interrupt vector number
Constant
Product register
Program memory
Repeat counter
3/4-bit shift value
Test-control bit
Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.
T P Meaning
0 0 BIO low
0 1 TC = 1
1 0 TC = 0
1 1 None of the above conditions
Temporary register n (n = 0, 1, or 2)
4-bit field representing the following conditions:
Z: ACC = 0
L: ACC < 0
V: Overflow
C: Carry
A conditional instruction contains two of these 4-bit fields. The 4-LSB field of the instruction is a 4-bit mask field. A 1 in the
corresponding mask bit indicates that the condition is being tested. The second 4-bit field (bits 4 – 7) indicates the state of
the conditions designated by the mask bits as being tested. For example, to test for ACC ≥ 0, the Z and L fields are set while
the V and C fields are not set. The next 4-bit field contains the state of the conditions to test. The Z field is set to indicate
testing of the condition ACC = 0, and the L field is reset to indicate testing of the condition ACC ≥ 0. The conditions possible
with these 8 bits are shown in the BCND and CC instructions. To determine if the conditions are met, the 4-LSB bit mask
is ANDed with the conditions. If any bits are set, the conditions are met.
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