SMJ320F240 Datasheet, PDF (26/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
clock generation (continued)
OSCBYP
ÁÁÁÁÁÁÁÁ _XTAL1/CLKIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _XTAL2
XTAL
OSC
ÁÁÁÁÁ_MUÁÁÁÁÁ_X
Div 2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Div 2}
PLL divide-by-2 bit
(CKCR1.3)
MUX
Phase
Detector
VCO
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _Feedback
ÁÁÁÁÁÁ _Divider
Div 1, 2, 3, 4, 5,
ÁÁÁÁÁÁ _{or 9}
ÁÁÁÁÁÁ ^PLL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Synchronizing CPUCLK}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ^{Clock Switch}
Clock Mode Bits
(CKCR0.7–6)
PLL multiply ratio
(CKCR1.2–0)
Clock Frequency and PLL Multiply Bits (CKCR1.7–4)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{1-MHz Clock Prescaler}
Prescale Bit (CKCR0.0)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{SYSCLK Prescaler Div 2 or 4}
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ _{Watchdog Clock Prescaler}
Figure 8. PLL Clock Module Block Diagram
ACLK
WDCLK
SYSCLK
low-power modes
The SMJ320F240 has four low-power modes (idle 1, idle 2, PLL power down, and oscillator power down). The
low-power modes reduce the operating power by reducing or stopping the activity of various modules (by
stopping their clocks). The two PLLPM bits of the clock module control register, CKCR0, select which of the
low-power modes the device enters when executing an IDLE instruction. Reset or an unmasked interrupt from
any source causes the device to exit from idle 1 low-power mode. A real-time interrupt from the watchdog timer
module causes the device to exit from all low-power modes except oscillator power down. This is a wake-up
interrupt. When enabled, reset or any of the four external interrupts (NMI, XINT1, XINT2, or XINT3) causes the
device to exit from any of the low-power modes (idle 1, idle 2, PLL power down, and oscillator power down).
The external interrupts are all wake-up interrupts. The maskable external interrupts (XINT1, XINT2, and XINT3)
must be enabled individually and globally to bring the device out of a low-power mode properly. It is, therefore,
important to ensure that the desired low-power-mode exit path is enabled before entering a low-power mode.
Figure 9 shows the wake-up sequence from a power down. Table 9 summarizes the low-power modes.
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