SMJ320F240 Datasheet, PDF (83/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
SPI slave mode timing parameters
Slave mode timing information is listed in the following tables.
SPI slave mode external timing requirements (clock phase = 0)^† (see Figure 44)
MIN
tc(SPC)S
Cycle time, SPICLK
8tc‡
tw(SPCH)S§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S – 70
tw(SPCL)S§
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S – 70
tw(SPCL)S§
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S – 70
tw(SPCH)S§
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S – 70
td(SPCH-SOMI)S§ Delay time, SPICLK high (clock polarity = 0) to SPISOMI valid
0.375tc(SPC)S – 70
td(SPCL-SOMI)S§ Delay time, SPICLK low (clock polarity = 1) to SPISOMI valid
0.375tc(SPC)S – 70
tv(SPCL-SOMI)S§ Valid time, SPISOMI data valid after SPICLK low (clock polarity =0)
0.75tc(SPC)S
tv(SPCH-SOMI)S§ Valid time, SPISOMI data valid after SPICLK high (clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCL)S§ Setup time, SPISIMO before SPICLK low (clock polarity = 0)
0
tsu(SIMO-SPCH)S§ Setup time, SPISIMO before SPICLK high (clock polarity = 1)
0
tv(SPCL-SIMO)S§ Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0)
0.5tc(SPC)S
tv(SPCH-SIMO)S§ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1)
0.5tc(SPC)S
† _{The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.}
‡ _{tc = system clock cycle time = 1 / SYSCLK = tc(SYS)}
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
MAX
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
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