SMJ320F240 Datasheet, PDF (46/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
serial communications interface (SCI) module (continued)
Frame Format and Mode
PARITY
EVEN/ODD ENABLE
SCICCR.6 SCICCR.5
TXWAKE
SCICTL1.3
1
WUT
SCITXBUF.7–0
Transmitter-Data
Buffer Register
8
TXSHF
Register
SYSCLK
SCIHBAUD. 15 – 8
Baud Rate
Register
(MSbyte)
SCILBAUD. 7 – 0
Baud Rate
Register
(LSbyte)
CLOCK ENA
SCICTL1.4
SCI TX Interrupt
TXRDY
TX INT ENA
SCICTL2.7
TX EMPTY
SCICTL2.0
SCICTL2.6
TXINT
TXENA
SCICTL1.1
SCITXD
External
Connections
SCIPC2.7–4
SCITXD
SCI PRIORITY LEVEL
1
Level 2 Int.
0
Level 1 Int.
SCI TX
PRIORITY
SCIPRI.6
Level 2 Int. ¹
Level 1 Int. ⁰
SCI RX
PRIORITY
SCIPRI.5
RXWAKE
SCIRXST.1
RX ERR INT ENA
SCICTL1.6
RX ERROR
SCIRXST.7 SCIRXST.4 – 2
RX ERROR FE OE PE
RXSHF
Register
SCIRXD
RXENA
SCICTL1.0
8
Receiver-Data
Buffer
Register
SCIRXBUF.7–0
SCI RX Interrupt
RXRDY RX/BK INT ENA
SCIRXST.6
BRKDT
SCIRXST.5
SCICTL2.1
SCIPC2.3–0
SCIRXD
Figure 14. Serial Communications Interface (SCI) Module Block Diagram
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