SMJ320F240 Datasheet, PDF (66/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
low-power mode timings (continued)
A0–A15
CLKOUT/IOPC1
td(IDLE–COH)
td(WAKE–A)
td(WAKE–LOCK)
WAKE INT
Figure 24. PLL Power-Down Entry and Exit Timings
A0–A15
CLKOUT/IOPC1
td(IDLE–OSC)
td(IDLE–COH)
td(WAKE–A)
td(WAKE–LOCK)
td(WAKE–OSC)
Á
WAKE INT
Figure 25. OSC Power-Down Entry and Exit Timings
memory and parallel I/O interface read timings
switching characteristics over recommended operating conditions for a memory read
(see Figure 26)
td(CO-A)RD
td(CO-SL)RD
td(CO-SH)RD
td(CO-ACTL)RD
td(CO-ACTH)RD
PARAMETER
Delay time, CLKOUT/IOPC1 low to address valid
Delay time, CLKOUT/IOPC1 low to STRB low
Delay time, CLKOUT/IOPC1 low to STRB high
Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR low
Delay time, CLKOUT/IOPC1 low to PS, DS, IS, and BR high
MIN MAX UNIT
17 ns
10 ns
6 ns
10 ns
10 ns
timing requirements for a memory read, H = 0.5t_c(CO)^† (see Figure 26)
ta(A)
Access time, from address valid to read data
0 wait state
1 wait state
tsu(D-COL)RD Setup time, data read before CLKOUT/IOPC1 low
th(COL-D)RD Hold time, data read after CLKOUT/IOPC1 low
† _{All timings with respect to CLKOUT/IOPC1 assume CLKSRC[1:0] bits are set to select CPUCLK for output.}
MIN MAX
2H – 32
4H – 32
15
2
UNIT
ns
ns
ns
66
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