SMJ320F240 Datasheet, PDF (63/99 Pages) Texas Instruments – DSP CONTROLLER

XTAL1/CLKIN
CLKOUT/IOPC1
tc(CI)
CLOCK OPTIONS (CONTINUED)
tw(CIH)
tw(CIL)
tr(CI)
tc(CO)
td(CIH–CO) ^tw(COH)
tf(CO)
tr(CO)
tw(COL)
SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
tf(CI)
Figure 20. External Divide-by-Two Clock Timings
external reference crystal with PLL-circuit-enabled clock option
The internal oscillator is enabled by connecting OSCBYP to V_DD and connecting a crystal across XTAL1/CLKIN
and XTAL2 pins as shown in Figure 19. The crystal should be in either fundamental or overtone operation and
W parallel resonant, with an effective series resistance of 30 and a power dissipation of 1 mW; it should be
specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned-LC circuit.
input characteristics with the PLL circuit enabled
fx
C1, C2
PARAMETER
Input clock frequency
Load capacitance
EXTERNAL REFERENCE
CRYSTAL
4 MHz
6 MHz
8 MHz
MIN TYP MAX UNIT
4
6
MHz
8
10
pF
switching characteristics over recommended operating conditions, H = 0.5 t_c(CO) (see Figure 21)
PARAMETER
CLOCK MODE
MIN
TYP MAX
UNIT
before PLL lock,
CLKIN divide by 2
2tc(Cl)
†
tc(CPU) _{Cycle time, CPUCLK}
before PLL lock,
CLKIN divide by 1
tc(Cl)
ns
after PLL lock
50
tc(SYS)
tc(CO)
Cycle time, SYSCLK
Cycle time, CLKOUT
CPUCLK divide by 2
CPUCLK divide by 4‡
2tc(CPU)
4tc(CPU)
50
†
ns
† ns
tf(CO)
Fall time, CLKOUT
5
ns
tr(CO)
Rise time, CLKOUT
5
ns
tw(COL) Pulse duration, CLKOUT low
H – 10
H–6
H – 1 ns
tw(COH) Pulse duration, CLKOUT high
H+0
H +4
H + 8 ns
before PLL lock,
tp
Transition time, PLL synchronized after PLL en- ^{CLKIN divide by 2}
abled
before PLL lock,
CLKIN divide by 1
2000tc(Cl)
ns
1000tc(Cl)
† _{This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is}
characterized at frequencies approaching 0 Hz.
‡ _{SYSCLK is initialized to divide-by-4 mode by any device reset.}
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