SMJ320F240 Datasheet, PDF (15/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
group1 shared I/O pins (continued)
SGUS029 – APRIL 1999
Table 2. Group1 Shared Pin Configurations
PIN #
MUX CONTROL
REGISTER
(name.bit #)
PIN FUNCTION SELECTED
(CRx.n = 1)
(CRx.n = 0)
72
OCRA.0
ADCIN0
IOPA0
73
OCRA.1
ADCIN1
IOPA1
90
OCRA.2
ADCIN9
IOPA2
91
OCRA.3
ADCIN8
IOPA3
100
OCRA.8
PWM7/CMP7
IOPB0
101
OCRA.9
PWM8/CMP8
IOPB1
102
OCRA.10
PWM9/CMP9
IOPB2
105
OCRA.11
T1PWM/T1CMP
IOPB3
106
OCRA.12
T2PWM/T2CMP
IOPB4
107
OCRA.13
T3PWM/T3CMP
IOPB5
108
OCRA.14
TMRDIR
IOPB6
109
OCRA.15
TMRCLK
IOPB7
63
OCRB.0
ADCSOC
IOPC0
64
SYSCR.7–6
00
IOPC1
01
WDCLK
10
SYSCLK
11
CPUCLK
65
OCRB.2
IOPC2
XF
66
OCRB.3
IOPC3
BIO
67
OCRB.4
CAP1/QEP1
IOPC4
68
OCRB.5
CAP2/QEP2
IOPC5
69
OCRB.6
CAP3
IOPC6
70
OCRB.7
CAP4
† _{Valid only if the I/O function is selected on the pin.}
IOPC7
I/O PORT DATA AND DIRECTION†
REGISTER
PADATDIR
PADATDIR
PADATDIR
PADATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PBDATDIR
PCDATDIR
DATA BIT #
0
1
2
3
0
1
2
3
4
5
6
7
0
DIR BIT #
8
9
10
11
8
9
10
11
12
13
14
15
8
PCDATDIR
1
9
—
—
—
—
—
—
—
—
—
PCDATDIR
2
10
PCDATDIR
3
11
PCDATDIR
4
12
PCDATDIR
5
13
PCDATDIR
6
14
PCDATDIR
7
15
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