SMJ320F240 Datasheet, PDF (75/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
PWM/CMP timings
PWM refers to PWM1/CMP1, PWM2/CMP2, PWM3/CMP3, PWM4/CMP4, PWM5/CMP5, PWM6/CMP6,
T1PWM/T1CMP, T2PWM/T2CMP, T3PWM/T3CMP, PWM7/CMP7, PWM8/CMP8, and PWM9/CMP9.
switching characteristics over recommended operating conditions for PWM timing (see Figure 33)
td(PWM)CO
PARAMETER
Delay time, CLKOUT high to PWM output switching
MIN MAX UNIT
12 ns
timing requirements, [H = 0.5t_c(CO)] (see Figure 34 and Figure 35)
tw(TMRDIR)
Pulse duration, TMRDIR low/high
tw(TMRCLKL)
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
tw(TMRCLKH)
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
tc(TMRCLK)
Cycle time, TMRCLK
† _{MIN value for ’C240 only}
MIN
4H + 12
4H + 14†
40
40
4 tc(CPU)
MAX
60
60
UNIT
ns
%
%
ns
CLKOUT/IOPC1
td(PWM)CO
PWM
Figure 33. PWM and Compare Output Timings
TMRCLK
tw(TMRCLKL)
tc(TMRCLK)
tw(TMRCLKH)
Figure 34. External Timer Clock Input Timings
TMRDIR
tw(TMRDIR)
Figure 35. External Timer Direction Input Timings
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