SMJ320F240 Datasheet, PDF (87/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
10-bit dual analog-to-digital converter (ADC)
The 10-bit dual ADC has a separate power bus for its analog circuitry. These pins are referred to as V_CCA and
V_SSA. The purpose is to enhance ADC performance by preventing digital-switching noise of the logic circuitry
that can be present on V_SS and V_CC from coupling into the ADC analog stage. All ADC specifications are given
with respect to V_SSA unless otherwise noted.
recommended operating conditions
MIN
NOM
VCCA
Analog supply voltage
4.5
5
VSSA
VREFHI
VREFLO
Analog ground
Analog supply reference source†
Analog ground reference source†
0
VREFLO
VSSA
VAI
Analog input voltage, ADCIN0–ADCIN15
VSSA
† _{VREFHI and VREFLO must be stable, within ±1/2 LSB of the required resolution, during the entire conversion time.}
MAX
5.5
VCCA
VREFHI
VCCA
UNIT
V
V
V
V
V
electrical characteristics (see Note 5)
PARAMETER
DESCRIPTION
MIN MAX UNIT
ICCA
Analog supply current
VCCA = 5.5 V
VCCA = VREFHI = 5.5 V
Converting
Non-converting
PLL or OSC power
down
5
2
mA
1
Iref
Input charge current, VREFHI or VREFLO
VCCA = VCCD = VREFHI = 5.5 V, VREFLO = 0 V
Cai
Analog input capacitance
Typical capacitive load on
analog input pin
Non-sampling
Sampling
5 mA
6
pF
8
ZAI
Analog input source impedance
Analog input source impedance for conversions to
remain within specifications.
9 kΩ
EDNL Differential nonlinearity error
Difference between the actual step width and the ideal
value
–1
1.5 LSB
EINL
Integral nonlinearity error
Maximum deviation from the best straight line through
the ADC transfer characteristics, excluding the
quantization error
"1.5 LSB
td(PU) Delay time, power-up to ADC valid
Time to stabilize analog stage after power-up
10 ms
NOTE 5: Absolute resolution = 4.89 mV. At VREFHI = 5 V and VREFLO = 0 V, this is one LSB. As VREFHI decreases, VREFLO increases, or both,
the LSB sizes decrease. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.
The ADC module allows complete freedom in the design of the sources for the analog inputs. The period of the
sample time is independent of the source impedance. The sample-and-hold period occurs in the first half-period
of the ADC clock after the ADCIMSTART bit or the ADCSOC bit of the ADC control register 1 (ADCTRL1, bits 13
and 0, respectively) is set to 1. The conversion then occurs during the next six ADC clock cycles. The digital
result registers are updated on the next ADC clock cycle once the conversion is completed.
ADC input pin circuit
One of the most common A/D application errors is inappropriate source impedance. In practice, minimum
source impedance should be used to limit the error as well as minimize the required sampling time; however,
the source impedance must be smaller than Z_AI. A typical ADC input pin circuit is shown in Figure 46.
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