SMJ320F240 Datasheet, PDF (36/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
dual-access RAM (DARAM) (continued)
The SETC CNF (configure B0 as data memory) and CLRC CNF (configure B0 as program memory) instructions
allow dynamic configuration of the memory maps through software. When using block 0 as program memory,
instructions can be downloaded from external program memory into on-chip RAM and then executed. When
using on-chip RAM, or high-speed external memory, the ’F240 runs at full speed with no wait states. The ability
of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the ’F240
architecture enables the device to perform three concurrent memory accesses in any given machine cycle.
Externally, the READY line can be used to interface the ’F240 to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.
flash EEPROM
Flash EEPROM provides an attractive alternative to masked program ROM. Like ROM, flash is a nonvolatile
 ^{memory type; however, it has the advantage of “in-target” reprogrammability. The SMJ320F240 incorporates}
one 16K 16-bit flash EEPROM module in program space. This type of memory expands the capabilities of
the SMJ320F240 in the areas of prototyping, early field-testing, and single-chip applications.
Unlike most discrete flash memory, the ’F240 flash does not require a dedicated state machine, because the
algorithms for programming and erasing the flash are executed by the DSP core. This enables several
advantages, including: reduced chip size and sophisticated, adaptive algorithms. For production programming,
the IEEE Standard 1149.1 (JTAG) scan port provides easy access to the on-chip RAM for downloading the
algorithms and flash code. Other key features of the flash include zero-wait-state access rate and single 5-V
power supply.
An erased bit in the SMJ320F240 flash is read as a logic 1, and a programmed bit is read as a logic 0. The flash
requires a block-erase of the entire 16K module; however, any combination of bits can be programmed. The
following four algorithms are required for flash operations: clear, erase, flash-write, and program. For an
explanation of these algorithms and a complete description of the flash EEPROM, see the TMS320F20x/F24x
DSPs Embedded Flash Memory Technical Reference (literature number SPRU282), which is available during
the 2nd quarter of 1998.
flash serial loader
The on-chip flash is shipped with a serial bootloader code programmed at the following addresses:
0x0000–0x00FFh. All other flash addresses are in an erased state. The serial bootloader can be used to
program the on-chip Flash memory with user’s code. During the Flash programming sequence, the on-chip data
RAM is used to load and execute the clear, erase, and program algorithms. See the TMS320F240 Serial
Bootloader application report (currently located at ftp://ftp.ti.com/pub/tms320bbs/c24xfiles/f240boot.pdf to
understand on-chip flash programming using the serial bootloader code. Look for further C2000 information
using the DSP link at www.ti.com.
flash control mode register
The flash control mode register is located at I/O address FF0Fh. This register offers two options: register access
mode and array access mode. Register access mode gives access to the four control registers in the memory
space decoded for the flash module. These registers are used to control erasing, programming, and testing of
the flash array. Register access mode is enabled by activating an OUT command with dummy data.
The OUT xxxx, FF0Fh instruction makes the flash registers accessible for reads and/or writes. After
executing OUT xxxx, FF0Fh, the flash control registers are accessed in the memory space decoded for the
flash module and the flash array cannot be accessed. The four registers are repeated every four address
locations within the flash module’s decoded range.
After completing all the necessary reads and/or writes to the control registers, an IN xxxx, FF0Fh instruction
(with dummy data) is executed to place the flash array back in array access mode. After executing the
IN xxxx, FF0Fh instruction, the flash array is accessed in the decoded space and the flash registers are
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