SMJ320F240 Datasheet, PDF (85/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
SPI slave mode external timing requirements (clock phase = 1)^† (see Figure 45)
MIN
tc(SPC)S
Cycle time, SPICLK
8tc‡
tw(SPCH)S§
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)S _{– 70}
tw(SPCL)S§
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)S _{– 70}
tw(SPCL)S§
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)S _{– 70}
tw(SPCH)S§
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)S _{– 70}
tsu(SOMI-SPCH)S§ Setup time, SPISOMI before SPICLK high (clock polarity = 0)
0.125tc(SPC)S
tsu(SOMI-SPCL)S§ Setup time, SPISOMI before SPICLK low (clock polarity = 1)
0.125tc(SPC)S
tv(SPCH-SOMI)S§ Valid time, SPISOMI data valid after SPICLK high (clock polarity =0)
0.75tc(SPC)S
tv(SPCL-SOMI)S§ Valid time, SPISOMI data valid after SPICLK low (clock polarity =1)
0.75tc(SPC)S
tsu(SIMO-SPCH)S§ Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
tsu(SIMO-SPCL)S§ Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
tv(SPCH-SIMO)S§ Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0)
0.5tc(SPC)S
tv(SPCL-SIMO)S§ Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1)
0.5tc(SPC)S
† _{The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.}
‡ _{tc = system clock cycle time = 1 / SYSCLK = tc(SYS)}
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
MAX
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
0.5tc(SPC)S
UNIT
ns
ns
ns
ns
ns
ns
ns
• POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443
85