SMJ320F240 Datasheet, PDF (81/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
SPI master mode external timing (clock phase = 1)^† (see Figure 43)
WHEN (SPIBRR + 1) IS EVEN OR
SPIBRR = 0 OR 2
WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
tc(SPC)M
tw(SPCH)M§
Cycle time, SPICLK
Pulse duration,
SPICLK high
(clock polarity = 0)
MIN
4tc‡
MAX
128tc‡
MIN
5tc‡
MAX
127tc‡
0.5tc(SPC)M – 70 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc – 70 0.5tc(SPC)M – 0.5tc
tw(SPCL)M§
Pulse duration,
SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – 70 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc – 70 0.5tc(SPC)M – 0.5tc
tw(SPCL)M§
Pulse duration,
SPICLK low (clock
polarity = 0)
0.5tc(SPC)M – 70 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc – 70 0.5tc(SPC)M + 0.5tc
tw(SPCH)M§
Pulse duration,
SPICLK high
(clock polarity = 1)
0.5tc(SPC)M – 70 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc – 70 0.5tc(SPC)M + 0.5tc
Setup time, SPISIMO
tsu(SIMO-SPCH)M§
data valid before
SPICLK high (clock
polarity = 0)
0.5tc(SPC)M – 70
0.5tc(SPC)M – 70
Setup time, SPISIMO
tsu(SIMO-SPCL)M§
data valid before
SPICLK low (clock
polarity = 1)
0.5tc(SPC)M – 70
0.5tc(SPC)M – 70
th(SPCH-SIMO)M§
Hold time, SPISIMO
data valid after
SPICLK high (clock
polarity =0)
0.5tc(SPC)M – 70
0.5tc(SPC)M – 70
th(SPCL-SIMO)M§
Hold time, SPISIMO
data valid after
SPICLK low (clock
polarity =1)
0.5tc(SPC)M – 70
0.5tc(SPC)M – 70
Setup time, SPISOMI
tsu(SOMI-SPCH)M§ before SPICLK high
0
0
(clock polarity = 0)
Setup time, SPISOMI
tsu(SOMI-SPCL)M§ before SPICLK low
0
0
(clock polarity = 1)
th(SPCH-SOMI)M§
Hold time, SPISOMI
data valid after
SPICLK high (clock
polarity = 0)
0.25tc(SPC)M – 70
0.5tc(SPC)M – 70
Hold time, SPISOMI
th(SPCL-SOMI)M§
data valid after
SPICLK low (clock
0.25tc(SPC)M – 70
0.5tc(SPC)M – 70
polarity = 1)
† _{The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set.}
‡ _{tc = system clock cycle time = 1 / SYSCLK = tc(SYS)}
§ _{The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).}
UNIT
ns
ns
ns
ns
ns
ns
ns
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