SMJ320F240 Datasheet, PDF (19/99 Pages) Texas Instruments – DSP CONTROLLER

hardware-generated interrupts (continued)
DSP Core
Address
Lines 5–1
IACK
INT6 INT5 INT4 INT3 INT2 INT1 NMI
SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
5
Address
Lines 5–1
IACK
NC NC NC
INT6 INT5 INT4 INT3 INT2 INT1 NMI
System Module
INTC INTB INTA
Event Manager
Figure 5. DSP Interrupt Structure
At the level of the system module and the event manager, each of the maskable interrupt lines (INT1–INT6) is
connected to multiple maskable interrupt sources. Sources connected to interrupt line INT1 are called Level 1
interrupts; sources connected to interrupt line INT2 are called Level 2 interrupts; and so on. For each interrupt
line, the multiple sources also have a set priority ranking. The source with the highest priority has its interrupt
request responded to by the DSP core first.
Figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. For each
interrupt chain, the interrupt source of highest priority is at the top. Priority decreases from the top of the chain
to the bottom. Figure 7 shows the interrupt sources and priority ranking for the event manager interrupts.
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