SMJ320F240 Datasheet, PDF (88/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
ADC input pin circuit (continued)
Requiv
R1
VIN
VAI (to ADCINx input)
R1 = 9 kΩ typical
Figure 46. Typical ADC Input Pin Circuit
ADC timing requirements (see Figure 47)
MIN MAX UNIT
tc(AD)
tw(SHC)
tw(SH)
Cycle time, ADC prescaled clock
Pulse duration, total sample/hold and conversion time (see Note 6)
Pulse duration, sample and hold time
1
ms
6.1
ms
tc(AD)
ms
tsu(SH)
Setup time, analog input stable before sample/hold start
0
ns
th(SH)
Hold time, analog input stable after sample/hold complete
0
ns
tw(C)
Pulse duration, total conversion time
4.5tc(AD)
ms
td(SOC-SH) Delay time, start of conversion† to beginning of sample and hold
3tc(SYS)
ns
td(EOC-FIFO) Delay time, end of conversion to data loaded into result FIFO
3tc(SYS)
ns
† _{Start of conversion is signaled by the ADCIMSTART bit or the ADCSOC bit set in software, the external start signal active (ADCSOC), or internal}
EVSOC signal active.
NOTE 6: The total sample/hold and conversion time is determined by the summation of td(SOC-SH), tw(SH), tw(C), and td(EOC-FIFO).
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