SMJ320F240 Datasheet, PDF (62/99 Pages) Texas Instruments – DSP CONTROLLER

SMJ320F240
DSP CONTROLLER
SGUS029 – APRIL 1999
CLOCK OPTIONS
clock options
PARAMETER
Clock-in mode, divide-by-2
Clock-in mode, divide-by-1
PLL enabled, divide-by-2 before PLL lock
PLL enabled, divide-by-1 before PLL lock
CLKMD[1:0]
00
01
10
11
input clock frequency over operating free-air temperature range (PLL circuit disabled)
PARAMETER
MIN MAX UNIT
Divide-by-2 mode
fx
Divide-by-1 mode
0†
40
0†
MHz
20
† _{This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is}
characterized at frequencies approaching 0 Hz.
switching characteristics over recommended operating conditions [H = 0.5 t_c(CO)]
(see Note 3 and Figure 20)
PARAMETER
CLOCK MODE
MIN
TYP MAX UNIT
tc(CPU)
Cycle time, CPUCLK
CLKIN divide by 2
CLKIN divide by 1
2tc(Cl)
tc(Cl)
†
ns
tc(SYS)
Cycle time, SYSCLK
CPUCLK divide by 2
CPUCLK divide by 4‡
2tc(CPU)
4tc(CPU)
†
ns
tc(CO)
Cycle time, CLKOUT
CLKIN divide by 2
CLKIN divide by 1
2tc(Cl)
tc(Cl)
†
ns
†
td(CIH-CO)
Delay time, XTAL1/CLKIN high to CLKOUT high/low
3
18
32 ns
tf(CO)
Fall time, CLKOUT
5
ns
tr(CO)
Rise time, CLKOUT
5
ns
tw(COL)
Pulse duration, CLKOUT low
H – 10
H – 6 H – 1 ns
tw(COH)
Pulse duration, CLKOUT high
H+0
H + 4 H +8 ns
† _{This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is}
characterized at frequencies approaching 0 Hz.
‡ _{SYSCLK is initialized to divide-by-4 mode by any device reset.}
NOTE 3: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.
timing requirements (see Figure 20)
CLOCK-IN MODE
MIN MAX UNIT
tc(Cl)
Cycle time, XTAL1/CLKIN
Divide by 2
Divide by 1
25
†
ns
50
†
tf(Cl)
Fall time, XTAL1/CLKIN
5 ns
tr(Cl)
Rise time, XTAL1/CLKIN
5 ns
tw(CIL)
Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)
45
55 %
tw(CIH)
Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)
45
55 %
† _{This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is}
characterized at frequencies approaching 0 Hz.
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